As semiconductor devices become more highly integrated, a distance between the source and the drain of a transistor should be optimized. However, as the channel area between the source and the drain becomes shorter due to the high integration of the drain, a short-channel effect may occur due to the shortened channel area. The short channel effect may cause a hot-carrier effect and a punch-through effect.
The hot-carrier effect indicates that carriers (electrons or holes) in a transistor channel of the semiconductor device may affect operational characteristics of the semiconductor device after acquiring high energy from an external electric field. In the case of the hot-carrier effect, the mobility of electrons may be higher than that of holes. This may cause the electron effect to imposes a negative influence upon operational characteristics of the semiconductor device as compared to the hole effect. The hot-carrier effect may deteriorate electric characteristics and reliability of the semiconductor device. Therefore, to reduce the short channel effect, a lightly doped drain (LDD) structure, which may have low-concentration impurity distribution, may be located between the drain area and the channel area, or the ion implantation process between the drain and the channel may be executed, which may minimize the hot-carrier effect or the punch-through effect.
FIG. 1 is a cross-sectional view illustrating a related art method of manufacturing a MOSFET of a semiconductor device.
Referring to FIG. 1, the gate oxide layer and the gate conductive layer may be sequentially formed on semiconductor substrate 100 including the shallow trench isolation (STI) layer (not shown). The gate conductive layer and the gate oxide layer may be etched to form gate electrode 101. Subsequently, the ion implantation of low concentration impurities may be executed on substrate 100, such that LDD area 102 may be formed in the surface of the active area of substrate 100 located at both sides of gate electrode 101. The insulation layer may be formed on the overall areas of semiconductor substrate 100 including gate electrode 101, and may be blanket-etched, such that spacer 103 may be formed on both sidewalls of gate electrode 101. Thereafter, an ion implantation of high concentration impurities may be executed on the resultant material, a thermal process may be then applied to the executed result, and source/drain area 104 may be formed in the surface of the substrate at sidewalls of gate electrode 101 including spacer 103, such that the MOSFET element may be completed.
The MOSFET element formed by the above-mentioned method employs the LDD structure and may improve the hot-carrier effect, and may restrain the hot-carrier effect. However, if unexpected problems occur in the ion implantation- or diffusion-process in the drain or source, operational characteristics of the MOSFET element may be unavoidably deteriorated by hot-carriers.